The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a novel method for a dual damascene process that uses a selected mask in the manufacture of integrated circuits. Merely by way of example, the invention can applied to a copper metal damascene structure such as a dual damascene structure used for advanced signal processing devices. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to microprocessor devices, logic circuits, application specific integrated circuit devices, as well as various other interconnect structures.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to form interchanging metal and dielectric layers, where the metal layers are not meant to interact with other metal layers in the form of noise.
As merely an example, aluminum metal layers have been the choice of material for semiconductor devices as such layers have been used in early integrated circuit devices. Aluminum provides good conductivity and adheres to dielectric materials as well as semiconductor materials. Most recently, however, aluminum metal layers have been replaced in part by copper interconnects. Copper interconnects have been used with low-k dielectric materials to form advanced conventional semiconductor devices. Copper possesses reduced resistance values compared to aluminum for propagating signals through the copper interconnect at high speeds. However, one significant problem that has occurred with the increasing use of copper interconnects is that copper is a much more difficult material than aluminum to etch and pattern because it does not form a volatile byproduct. Thus, copper metallization schemes cannot be used with conventional subtractive etching procedures used for aluminum. Dual damascene processes have been used instead of conventional metallization schemes whereby the interconnect trench and via are formed within the same sequence of process steps and a chemical-mechanical planarization step (CMP) is used to remove the overfill of deposited material in the trench and via. While dual damascene processes have reduced the number of steps used in the process sequence, even greater simplification could be implemented to reduce complexity of the dual-damascene process being employed.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.